DPAD10 [Linear Systems]

MONOLITHIC DUAL PICO AMPERE DIODES; 单片双PICO安培二极管
DPAD10
型号: DPAD10
厂家: Linear Systems    Linear Systems
描述:

MONOLITHIC DUAL PICO AMPERE DIODES
单片双PICO安培二极管

二极管
文件: 总2页 (文件大小:195K)
中文:  中文翻译
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DPAD SERIES  
MONOLITHIC DUAL  
Linear Integrated Systems  
PICO AMPERE DIODES  
FEATURES  
Direct Replacement For SILICONIX DPAD SERIES  
HIGH ON ISOLATION  
DPAD1  
DPAD  
20fA  
TO-72  
TO-78  
EXCELLENT CAPACITANCE MATCHING  
ABSOLUTE MAXIMUM RATINGS1  
@ 25 °C (unless otherwise stated)  
Maximum Temperatures  
CR 0.2pF  
BOTTOM VIEW  
BOTTOM VIEW  
C
4
3
1
5
7
A1  
K1  
A2  
K2  
3
1
5
7
A1  
K1  
K2  
A2  
Storage Temperature  
-65 to +150 °C  
-55 to +135 °C  
SSTDPAD  
Operating Junction Temperature  
Maximum Power Dissipation  
Continuous Power Dissipation (DPAD)  
Maximum Currents  
SOIC  
1
2
3
4
8
7
6
5
K1  
K2  
K2  
A2  
NC  
K1  
A1  
500mW  
50mA  
NC  
Forward Current (DPAD)  
COMMON ELECTRICAL CHARACTERISTICS @ 25 °C (unless otherwise stated)  
SYMBOL  
CHARACTERISTIC  
MIN TYP MAX UNITS CONDITIONS  
DPAD1  
DPAD2,5,10,20,50,100 -45  
SSTDPAD5,50,100  
-45  
Reverse Breakdown  
Voltage  
BVR  
IR = -1µA  
IF = 1mA  
V
-30  
VF  
Forward Voltage  
0.8  
1.5  
0.2  
0.5  
0.8  
2.0  
4.0  
DPAD1  
ALL OTHERS  
DPAD1  
DPAD2,5,10,20,50,100  
SSTDPAD5,50,100  
Differential Capacitance  
|CR1-CR2|  
VR1 = VR2 = -5V, f = 1MHz  
(CR)  
pF  
Crss  
Total Reverse Capacitance  
VR = -5V, f = 1MHz  
CONDITIONS  
VR = -20V  
SPECIFIC ELECTRICAL CHARACTERISTICS @ 25 °C (unless otherwise stated)  
SYMBOL CHARACTERISTIC  
DPAD2  
-1  
SSTDPAD2  
UNITS  
(SST)DPAD1  
(SST)DPAD2  
(SST)DPAD5  
(SST)DPAD10  
(SST)DPAD20  
(SST)DPAD50  
(SST)DPAD100  
-2  
-5  
-5  
Maximum Reverse  
IR  
pA  
-10  
-20  
-50  
-100  
Leakage Current2  
-50  
-100  
Linear Integrated Systems • 4042 Clipper Court • Fremont, CA 94538 • Tel: 510 490-9160 • Fax: 510 353-0261  
Figure 1. Operational Amplifier Protection  
Input Differential Voltage limited to 0.8V (typ) by DPADs D1 and D2. Common  
Mode Input voltage limited by DPADs D3 and D4 to ±15V.  
Figure 2. Sample and Hold Circuit  
Typical Sample and Hold circuit with clipping. DPAD diodes reduce offset  
voltages fed capacitively from the JFET switch gate.  
FIGURE 1  
FIGURE 2  
+V -V  
+V  
DPAD10  
DPAD1  
D1  
D2  
-
D1  
D3  
D2  
D4  
OP-27  
+
2N4117A  
2N4393  
ein  
CONTROL  
SIGNAL  
C
VOUT  
+15V -15V  
R
TO-78  
SOIC  
TO-72  
Four Lead  
0.335  
0.014  
0.018  
0.230  
1
2
3
4
8
7
6
5
0.370  
DIA.  
0.050  
0.305  
0.195  
0.175  
0.209  
DIA.  
0.335  
0.189  
0.196  
MAX.  
0.030  
MAX.  
0.165  
0.185  
0.040  
0.150  
0.115  
0.021  
0.016  
0.019  
DIM. A  
MIN. 0.500  
0.150  
0.157  
4 LEADS  
0.016  
0.021  
DIM. B  
0.500 MIN.  
0.050  
SEATING  
PLANE  
0.019  
0.016  
DIA.  
0.0040  
0.0098  
0.200  
0.100  
0.100  
0.029  
0.045  
0.0075  
0.0098  
0.2284  
0.2440  
3
7
4
5
2
4
1
DIMENSIONS IN  
INCHES  
1
3
0.100  
45°  
45°  
0.028  
0.034  
0.046  
0.036  
0.048  
0.028  
1. Absolute maximum ratings are limiting values above which serviceability may be impaired.  
2. The DPAD type number denotes its maximum reverse current value in pico amperes. Devices with IR values intermediate to those  
shown are available upon request.  
Information furnished by Linear Integrated Systems is believed to be accurate and reliable. However, no responsibility is assumed for its  
use; nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or  
otherwise under any patent or patent rights of Linear Integrated Systems.  
Linear Integrated Systems • 4042 Clipper Court • Fremont, CA 94538 • Tel: 510 490-9160 • Fax: 510 353-0261  

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